The present invention relates to multiplexers used in computer systems and more particularly to a multiplexer comprising an important number of asynchronous channels which can function at different transmission speeds.
FIG. 1 shows a simplified schematic diagram of a multiplexer in a computer system. The elements of the multiplexer are included between two vertical dashed lines. The multiplexer comprises a plurality of UARTs (Universal Asynchronous Receiver/Transmitters) 10 connected through serial communication lines, such as RS232 lines, to exterior elements 12 such as terminals, peripherals or other computer systems. A first-in first-out (FIFO) buffer 14 is associated to each of the UARTs. Hereinafter, a group including a serial connection, a UART, and a FIFO will be called a channel C and only the case where the exterior elements 12 transmit data will be studied.
A data and address bus B interconnects each channel, with a microprocessor (CPU) 16, a memory (RAM) 18, and an interface circuit (BIC) 20 between bus B and an external bus of the computer system.
It can be considered that in the FIFOs, data are piled up by order of arrival, the bottom datum (the first one) being withdrawn from the pile and presented on the data bus when the FIFO is read-selected by an address. The read data is then transferred to the RAM 18 before it is transferred to the external bus. It will be supposed hereinafter that the data are characters.
The communication protocol of each of the channels, especially the transmission speed, is determined by a register (not shown) of the associated UART, which can be programmed through bus B. The transmission speed is given by a signal F provided to each UART by a clock circuit (CK) 22 which can eventually provide an additional signal 12 of programmable frequency. It is usual to have a transmission speed comprised between 300 bauds and 38.4 kilobauds. This transmission speed, hereinafter channel speed, can attain the frequency of signal F. The slower transmission speeds are obtained in the UARTs from signal F by dividing its frequency by powers of 2.
Presently, it is attempted to increase the number of channels and/or the maximum transmission speed without increasing the power of the microprocessor, that is the frequency at which the microprocessor functions, or to choose a less powerful microprocessor for a given number of channels. This is attempted knowing that the multiplexer will be unable to manage all the channels if the latter all receive characters at the maximum speed, but also knowing that it is more likely to only have a limited number of channels operating at high speed. It will be supposed hereinafter that the multiplexer is in this more realistic situation.
The incapacity of managing the channels results in an overflow of the FIFOs due to the fact that the microprocessor does not have the time to transfer the characters into the RAM, or results in an overflow of the RAM due to the fact that the microprocessor does not have the time to transfer the characters to the external bus. When a FIFO overflow occurs, the corresponding UART transmits to the associated circuit 12 a signal, Xoff, indicating to the latter that it must stop transmitting. In general, signal Xoff is sent as soon as a predetermined fraction of the FIFO is filled in order to leave a security margin, because circuit 12 could still transmit a few characters after receiving signals Xoff or even ignore this signal if the circuit is designed to not use this signal. The FIFOs are generally of small size, for example 16 characters, and signal Xoff is sent as soon as a FIFO is half full.
The multiplexer of FIG. 1 can conventionally operate according to one of three modes according to the programming of the UARTs, and of clock CK (for the third mode).
A first mode is an interrupt per character mode. In this mode, as soon as a character arriving on a channel is written in the corresponding FIFO, the UART asserts an interrupt request I1 which is provided to an interruption input IRQ of the microprocessor through an OR gate 24. At the same time, the UART writes in a not shown register data corresponding to the number of the channel. Then the microprocessor interrupts its task, reads in the above register the number of the channel to process, and polls the corresponding channel. By polling a channel, it is understood that it is checked whether the corresponding FIFO is empty and, if not, transferring its content to the RAM.
FIG. 2 symbolically shows processing durations according to this first mode. Characters arrive at random moments t. From a moment t, an interruption is generated and an interruption processing time interval Tf is started. At the end of interval Tf, a character processing interval Tc starts. If a character arrives when the preceding character has not yet been processed, the interruption is memorized and is processed at the end of interval Tc of the preceding character.
This first operating mode is very disadvantageous. Indeed, the interruption processing time Tf is such greater than the character processing time Tc. For example, if the microprocessor is a series 68000 of MOTOROLA operating at 16 MHz, time Tf is approximately equal to 4Tc. Furthermore, the arrival of a character in the FIFO of a channel operating at a maximum frequency of 38.4 kilobauds is greater that Tf+Tc; hence, for a same interruption, only one character at the time can be processed. Thus, supposing that a continuous flow of characters arrives on the channels, the processing efficiency of the characters is EQU Tc/(Tf+Tc).apprxeq.1/5.
A second possible operating mode is the continuous mode. In this mode, the UARTs do not send interruptions and the microprocessor executes in an endless loop a main program comprising a sub-program for polling all the channels. It is chosen, either by inserting delays in the main program if the execution time of the latter is too short, either by multiplying the number of polling sub-programs in the main program if the execution time of the latter is too long, to render the means time Te elapsed between two polls substantially equal to the time its takes to fill a FIFO at the maximum transmission speed to the point an Xoff signal is sent. Hereinafter, this time will be called "minimum time for partial filling". This time Te thus varies from one poll to the other as a function of the amount of tasks to be done by the microprocessor in the main program and in the subprogram(s).
FIG. 3 symbolically shows the time elapsed during the execution of the loops of the main program. It is supposed in this figure that the main program comprises one polling subprogram which is executed at the start of the main program. Moments t0, t1 and t2 are shown indicating the beginning of each main program execution.
At moment t0, the character flow on the channel is low, the execution time .SIGMA.T of the sub-program is low as well as the total time Te=t1-t0 for executing the loop as the main program is then only essentially in charge of transferring a low number of characters stored in the RAM to the external bus.
At moment t1, it is supposed that the character flow is more important. Not only time .SIGMA.T increases, but also the transferring time of the characters from the RAM to the external bus. Thus, the time increase of interval Te=t2-t1 is greater than the only time increase of interval .SIGMA.T.
This second operating mode is much more convenient than the previous one because the microprocessor must not process interruptions. However, if the character flow is great, time Te can become greater than the minimum time of partial, or even total, filling. In this case, a FIFO of a maximum speed channel overflows, or at least, attains the filling state which causes a signal Xoff to be sent, which is tried to be avoided.
A third operating mode is a periodical interruption mode. This operating mode is similar to the previous one, except that the polling sub-programs are periodically executed. In order to achieve this, an interruption signal 12 is provided to the microprocessor, the period of which is equal to the minimum time of partial filling of a FIFO. This interruption signal 12, as shown in FIG. 1, is provided by clock CK to the input IRQ of the microprocessor through OR gate 24. The frequency of the interruption signal 12 is obtained by dividing the frequency of signal F by a factor which can be programmed in the clock circuit through bus B.
FIG. 4 symbolically shows a period T.sub.1 of interruption signal 12. This period is sub-divided in a plurality of time intervals. At the beginning of the period, a constant time interval Tf starts. This time interval corresponds to the interruption processing time by the microprocessor. This time interval is followed by time intervals T1, T2. . . Tn corresponding respectively to the polling of each of the channels Cl to Cn. The intervals T1 to Tn, the sum of which is equal to .SIGMA.T, are each sub-divided in a constant time interval Ts which corresponds to the time necessary for selecting a channel and in a time interval .SIGMA.Tc which is the sum of the times Tc for treating the characters stored in the FIFO of the channel. A variable time interval Tr occupying the remaining of period T.sub.I, is the time remaining for the microprocessor to achieve its other tasks, especially transferring the characters from the RAM to the external bus. When interval Tr is sufficiently great, the microprocessor can at each period transfer the whole content of the RAM to the external bus. But if it is too small, this transfer must be distributed on a plurality of periods, hoping that the RAM does not continue to fill too quickly.
With respect to the previous mode, this operating mode has, for each period T.sub.I, an additional inactivity time Tf corresponding to the processing of an interruption. This operating mode is thus slightly less efficient than the previous one but it is more reliable because period T.sub.I does not vary. The means character processing efficiency with respect to a period T.sub.I is expressed by ##EQU1## wherein n designates the number of channels and m the mean number of characters arriving per period. It will be noted that this efficiency increases with m and thus that its value is the greatest when all channels receive characters at maximum speed. This mode happens to be the most efficient when all channels are operating at maximum speed.
However, as previously mentioned, it is much more likely that a limited number (eventually null) of the channels operate at maximum speed, the other channels operating at lower speeds. Then, the above efficiency decreases substantially and represents an obstacle if it is desired to increase the number of channels. If it is supposed, for example, that channel C1 corresponding to interval T1 operates at maximum frequency, that period T.sub.I corresponds to the arrival of 8 characters at this frequency in the FIFO, and that channel C2 corresponding to interval T2 operates at a speed 8 times smaller than the maximum speed, at each period T.sub.I, 8 characters will be processed during interval T1 and only one during interval T2. Actually, an interval Ts will have been spent for 8 characters and an additional interval Ts will have been spent for one character. If other channels operate at still smaller speed, additional intervals Ts will be spent for no characters. It will be noted that, in such a case, term n.multidot.TS in the expression of the efficiency r increases with respect to terms m.multidot.Tc, which causes a decrease of the efficiency.
Thus, the more channels there are operating at low speeds with respect to channels operating at high speeds, the more the character processing efficiency decreases and the more the possibility of managing additional channels is diminished.